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publication number 30167 revision a amendment +1 issue date june 9, 2004 preliminary information s25fl family (serial peripheral interface) s25fl002d, S25FL001D 2 megabit, 1 megabit cmos 3.0 volt flash memory with 25 mhz spi bus interface distinctive characteristics architectural advantages ? single power supply operation ? full voltage range: 2.7 to 3.6 v read and program operations ? memory architecture ? 2 mb ? four sectors with 512 kb each ? 1 mb ? four sectors with 256 kb each ? program ? page program (up to 256 bytes) in 6 ms (typical) ? program cycles are on a page by page basis ? erase ? 0.25 s typical sector erase time (S25FL001D) ? 0.5 s typical sector erase time (s25fl002d) ? 1.0 s typical bulk erase time (S25FL001D) ? 2.0 s typical bulk erase time (s25fl002d) ? endurance ? 100,000 cycles per sector typical ? data retention ? 20 years typical ? device id ? electronic signature ? process technology ? manufactured on 0.25 m process technology ? package option ? industry standard pinouts ? 150 mil 8-pin so package for 1mb and 2mb ? 208 mil 8-pin so package for 2mb only ? 8-contact wson leadless package (6x5 mm) performance characteristics ? speed ? 25 mhz clock rate (maximum) ? power saving standby mode ? standby mode 1 a (typical) memory protection features ? memory protection ? w# pin works in conjunction with status register bits to protect specified memory areas ? status register block protection bits (bp1, bp0) in status register configure parts of memory as read- only software features ? spi bus compatible serial interface
2 s25fl family (serial peripheral interface) 30167a+1 june 9, 2004 preliminary information general description the s25fl002d and S25FL001D devices are 3.0 volt (2.7 v to 3.6 v) single power supply flash memory devices. s25fl002d consists of four sectors, each with 512 kb memory. S25FL001D consists of four sectors, each with 256 kb memory. data appears on si input pin when inputting data into the memory and on the so output pin when outputting data from the memory. the devices are designed to be programmed in-system with the standard system 3.0 volt v cc supply. the memory can be programmed 1 to 256 bytes at a time, using the page program in - struction. the memory supports sector erase and bulk erase instructions. each device requires only a 3.0 volt power supply (2.7 v to 3.6 v ) for both read and write functions. internally generated and regulated voltages are provided for the program operations. this device does not require v pp supply.
june 9, 2004 30167a+1 s25fl family (serial peripheral interface) 3 preliminary information table of contents block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 connection diagrams . . . . . . . . . . . . . . . . . . . . . . .5 input/output descriptions . . . . . . . . . . . . . . . . . . . 5 logic symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 ordering information . . . . . . . . . . . . . . . . . . . . . . . .6 signal description . . . . . . . . . . . . . . . . . . . . . . . . . . .7 spi modes ...................................................................................................7 figure 1. bus master and memory devices on the spi bus ....... 8 figure 2. spi modes supported ............................................ 8 operating features . . . . . . . . . . . . . . . . . . . . . . . . .9 page programming .................................................................................. 9 sector erase, or bulk erase ................................................................. 9 polling during a write, program, or erase cycle ........................ 9 status register ......................................................................................... 9 protection modes ..................................................................................10 table 1. protected area sizes (s25fl002d). .........................10 table 2. protected area sizes (S25FL001D). .........................10 hold condition modes ........................................................................10 figure 3. hold condition activation...................................... 11 memory organization . . . . . . . . . . . . . . . . . . . . . . 12 table 3. sector address table ? s25fl002d .........................12 table 4. sector address table ? S25FL001D .........................12 instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 table 5. instruction set. ....................................................13 write enable (wren) ..........................................................................14 figure 4. write enable (wren) instruction sequence............. 14 write disable (wrdi) ........................................................................ 14 figure 5. write disable (wrdi) instruction sequence ............ 14 read status register (rdsr) ............................................................. 14 figure 6. read status register (rdsr) instruction sequence .. 15 figure 7. status register format......................................... 15 write status register (wrsr) .......................................................... 16 figure 8. write status register (wrsr) instruction sequence . 16 table 6. protection modes ..................................................17 read data bytes (read) .................................................................... 17 figure 9. read data bytes (read) instruction sequence ........ 18 read data bytes at higher speed (fast_read) ....................... 18 figure 10. fast read (fast_read) instruction sequence ....... 19 page program (pp) ................................................................................. 19 figure 11. page program (pp) instruction sequence.............. 20 sector erase (se) .................................................................................. 20 figure 12. sector erase (se) instruction sequence ............... 21 bulk erase (be) ....................................................................................... 21 figure 13. bulk erase (be) instruction sequence .................. 22 software protect (sp) ......................................................................... 22 figure 14. software protection (sp) instruction sequence...... 23 release from software protect (res) .............................................23 figure 15. release from software protect (res) instruction sequence ........................................................................ 24 release from software protection and read electronic signature (res), and read id (read_id) ....................................................... 24 figure 16. release from software protection and read electronic signature (res), and read id (read_id) instruction sequence ........................................................................ 25 power-up and power-down . . . . . . . . . . . . . . . . . 26 figure 17. power-up timing............................................... 26 table 7. power-up timing ................................................. 27 initial delivery state . . . . . . . . . . . . . . . . . . . . . . . 27 maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . 27 absolute maximum ratings . . . . . . . . . . . . . . . . . 27 operating ranges . . . . . . . . . . . . . . . . . . . . . . . . . . 27 dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . 28 test conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 figure 18. ac measurements i/o waveform......................... 29 table 8. test specifications ............................................... 29 table 9. ac characteristics ................................................ 30 figure 19. spi mode 0 (0,0) input timing ............................ 31 figure 20. spi mode 0 (0,0) output timing.......................... 31 figure 21. hold# timing.................................................. 32 figure 22. write protect setup and hold timing during wrsr when srwd=1 ....................................................... 32 physical dimensions . . . . . . . . . . . . . . . . . . . . . . . 33 s08 narrow?8-pin plastic small outline 150mils body width package ............................................................................33 s08 wide?8-pin plastic small outline 208mils body width package ............................................................................34 8-contact wson (6mm x 5mm) leadless package .................36
4 s25fl family (serial peripheral interface) 30167a+1 june 9, 2004 preliminary information block diagram sck si so gnd v cc w# hold# sram ps logic array - l array - r rd data path io x d e c cs#
june 9, 2004 30167a+1 s25fl family (serial peripheral interface) 5 preliminary information connection diagrams note: 1. 8-pin plastic small outline package (208 mils) offered for 2mb density only. input/output descriptions sck = serial clock input si = serial data input so = serial data output cs# = chip select input w# = write protect input hold# = hold input v cc = supply voltage input gnd = ground input logic symbol 1 2 3 4 8 7 6 5 cs# so w# gnd si sck hold# v cc 1 2 3 4 8 7 6 5 cs# so w# gnd si sck hold# v cc 8-pin plastic small outline package (so) 8-contact wson package cs# so w# gnd si sck hold# v cc
6 s25fl family (serial peripheral interface) 30167a+1 june 9, 2004 preliminary information ordering information the order number (valid combination) is formed by the following: notes: 1. type 1 is standard. specify other options as required. 2. contact your local sales office for availability. 3. package marking omits leading ?s25? and speed, package, and leading digit of model number from ordering part number. 4. if ?last digit of model number? is ?2?, then this signifies a lead (pb)-free package. for example: fl002di2 if ?last digit of model number? is ?0?, this signified a standard package. for example: fl002di0. valid combinations valid combinations list configurations planned to be supported in volume for this device. s25fl 002 d 0f m a i 00 i packing type 1 = tube (standard; see note 1) 3 = 13? tape and reel (note 2) model number (additional ordering options) 00 = s0-8 narrow (150 mils) package 01 = s0-8 wide (208 mils) package temperature range i = industrial (?40 c to +85 c) package materials a=standard f = lead (pb)-free (note 2) package type m = 8 pin plastic small outline package n=wson (note 2) speed 0f = 25 mhz device technology d = 0.25 m process technology density 002 = 2 mb 001 = 1 mb device family spansion tm memory 3.0 volt-only, serial peripheral interface (spi) flash memory s25fl valid combinations package marking (note 3) base ordering part number speed option package & temperature model number packing type s25fl002d 0f mai, mfi, nfi 00, 01 1, 3 (note 1) fl002d + (temp) + (last digit of model number) (note 4) S25FL001D 00 fl001d + (temp) + (last digit of model number) (note 4)
june 9, 2004 30167a+1 s25fl family (serial peripheral interface) 7 preliminary information signal description signal data output (so): this output signal is used to transfer data serially out of the device. data is shifted out on the falling edge of serial clock (sck). serial data input (si): this input signal is used to transfer data serially into the device. it receives instructions, add resses, and the data to be programmed. values are latched on the rising edge of serial clock (sck). serial clock (sck): this input signal provides the timing of the serial interface. instructions, addresses, and data present at the serial data input (si) are latched on the rising edge of serial clock (sck). data on serial data output (so) changes after the falling edge of serial clock (sck). chip select (cs#): when this input signal is high , the device is deselected and serial data output (so) is at high impedance. unless an internal program, erase or write status register cycle is in progress, the device will be in standby mode. driving chip select (cs#) low enables the device, placing it in the active power mode. after power-up, a falling edge on chip select (cs#) is required prior to the start of any instruction. hold (hold#): the hold (hold#) signal is used to pause any serial communi - cations with the device without deselecting the device. during the hold instruction, the serial da ta output (so) is high impedance, and serial data input (si) and s erial clock (sck) are don?t care. to start the hold condition, the device must be selected, with chip select (cs#) driven low. write protect (w#): the main purpose of this input signal is to freeze the size of the area of memory that is protected against program or erase instructions (as specified by the values in the bp1 and bp0 bits of the status register). spi modes these devices can be driven by a micro co ntroller with its spi peripheral running in either of the two following modes: ? cpol = 0, cpha = 0 ? cpol = 1, cpha = 1 for these two modes, input data is latched in on the rising edge of serial clock (sck), and output data is available from the falling edge of serial clock (sck). the difference between the two modes, as shown in figure 2 , is the clock polarity when the bus master is in standby and not transferring data: ? sck remains at 0 for (cpol = 0, cpha = 0) ? sck remains at 1 for (cpol = 1, cpha = 1)
8 s25fl family (serial peripheral interface) 30167a+1 june 9, 2004 preliminary information figure 1. bus master and memory devices on the spi bus note: the write protect (w#) and hold (hold#) signals should be driven, high or low as appropriate. figure 2. spi modes supported spi interface with (cpol, cpha) = (0, 0) or (1, 1) bus master cs3 cs2 cs1 spi memory device spi memory device spi memory device cs# w# hold# cs# w# hold# cs# w# hold# sck so si sck so si sck so si so si sck msb msb sck sck si so cpha cpol 00 11 cs#
june 9, 2004 30167a+1 s25fl family (serial peripheral interface) 9 preliminary information operating features all data into and out of the device is shifted in 8-bit chunks. page programming to program one data byte, two instructions are required: write enable (wren), which is one byte, and a page program (pp) sequence, which consists of four bytes plus data. this is followed by the internal program cycle. to spread this overhead, the page program (pp) instruction allows up to 256 bytes to be pro - grammed at a time (changing bits from 1 to 0), provided that they lie in consecutive addresses on th e same page of memory. sector erase, or bulk erase the page program (pp) instruction allows bits to be programmed from 1 to 0. be - fore this can be applied, the bytes of the memory need to be first erased to all 1?s (ffh) before any programming. this can be achieved in two ways: 1) a sector at a time using the sector erase (se) instruction, or 2) throughout the entire memory, using the bulk erase (be) instruction. polling during a write, program, or erase cycle a further improvement in the time to write status register (wrsr), program (pp) or erase (se or be) can be achieved by not waiting for the worst-case delay. the write in progress (wip) bit is provided in the status register so that the applica - tion program can monitor its value, polling it to establish when the previous write cycle, program cycle, or erase cycle is complete. active power and standby power modes when chip select (cs#) is low, the device is enabled, and in the active power mode. when chip select (cs#) is high, the device is disabled, but could remain in the active power mode until all internal cycles have completed (program, erase, write status register). the device then goes into the standby power mode. the device consumption drops to i sb . this can be used as an extra soft - ware protection mechanism, wh en the device is not in active use, to protect the device from inadvertent write, program, or erase instructions. status register the status register contains a number of status and control bits, as shown in fig - ure 7 , that can be read or set (as appr opriate) by specific instructions ? wip bit: the write in progress (wip) bit indicates whether the memory is busy with a write status register, program or erase cycle. ? wel bit: the write enable latch (wel) bit indicates the status of the internal write enable latch. ? bp1, bp0 bits: the block protect (bp1, bp0) bits are non-volatile. they de- fine the size of the area to be soft ware protected against program and erase instructions. ? srwd bit: the status register write disable (srwd) bit is operated in con- junction with the write protect (w#) signal. the status register write disable (srwd) bit and write protect (w#) signal allow the device to be put in the hardware protected mode. in this mode, the non-volatile bits of the status register (srwd, bp1, bp0) become read-only bits.
10 s25fl family (serial peripheral interface) 30167a+1 june 9, 2004 preliminary information protection modes the spi memory device boasts the following data protection mechanisms: ? all instructions that modify data must be preceded by a write enable (wren) instruction to set the write enable latch (wel) bit. this bit is returned to its reset state by the following events: ?power-up ? write disable (wrdi) instruction completion ? write status register (wrsr) instruction completion ? page program (pp) instruction completion ? sector erase (se) instruction completion ? bulk erase (be) instruction completion ? the block protect (bp1, bp0) bits allow part of the memory to be configured as read-only. this is the software protected mode (spm). ? the write protect (w#) signal works in cooperation with the status register write disable (srwd) bit to enable write-protection. this is the hardware protected mode (hpm). ? program, erase and write status register instructions are checked to verify that they consist of a number of clock pulses that is a multiple of eight, before they are accepted for execution. ta b l e 1 . protected area sizes (s25fl002d). ta b l e 2 . protected area sizes (S25FL001D). note:the device is ready to accept a bulk erase (be) instruction, if and only if, both block protect (bp1 and bp0) are 0. hold condition modes the hold (hold#) signal is used to pa use any serial communications with the device without resetting the clocking se quence. hold (hold#) signal gates the clock input to the device. however, taking this signal low does not terminate any write status register, program or erase cycle that is currently in progress. protected memory area status register content memory content bp1 bit bp0 bit protected area unprotected area 0% 0 0 none 00000?3ffff 25% 0 1 30000?3ffff 00000?2ffff 50% 1 0 20000?3ffff 00000?1ffff 100% 1 1 00000?3ffff none protected memory area status register content memory content bp1 bit bp0 bit protected area unprotected area 0% 0 0 none 00000?1ffff 25% 0 1 18000?1ffff 00000?17fff 50% 1 0 10000?1ffff 00000?0ffff 100% 1 1 00000?1ffff none
june 9, 2004 30167a+1 s25fl family (serial peripheral interface) 11 preliminary information to enter the hold condition, the device must be selected, with chip select (cs#) low. the hold condition starts on the falling edge of the hold (hold#) signal, provided that this coincides with serial clock (sck) being low (as shown in figure 3 ). the hold condition ends on the rising edge of the hold (hold#) signal, provided that this coincides with serial clock (sck) being low. if the falling edge does not coincide with serial clock (sck) being low, the hold condition starts after serial clock (sck) next goes low. similarly, if the rising edge does not coincide with serial clock (sck) being low, the hold condition ends after serial clock (sck) next goes low ( figure 3 ). during the hold condition, the serial data output (so) is high impedance, and serial data input (si) and serial clock (sck) are don?t care. normally, the device remains selected, with chip select (cs#) driven low, for the entire duration of the hold condition. this ensures that the state of the internal logic remains unchanged from the moment of entering the hold condition. note: driving chip select (cs#) high while hold# is still low is not a valid operation. figure 3. hold condition activation sck hold# hold condition (standard use) hold condition (non-standard use)
12 s25fl family (serial peripheral interface) 30167a+1 june 9, 2004 preliminary information memory organization the memory is organized as: ? s25fl002d: four sectors of 512 kbit each ? S25FL001D: four sectors of 256 kbit each ? each page can be individually programmed (bits are programmed from 1 to 0). ? the device is sector, or bulk erasable (bits are erased from 0 to 1). ta b l e 3 . sector address table ? s25fl002d ta b l e 4 . sector address table ? S25FL001D sector address range sa3 30000h 3ffffh sa2 20000h 2ffffh sa1 10000h 1ffffh sa0 00000h 0ffffh sector address range sa3 18000h 1ffffh sa2 10000h 17fffh sa1 08000h 0ffffh sa0 00000h 07fffh
june 9, 2004 30167a+1 s25fl family (serial peripheral interface) 13 preliminary information instructions all instructions, addresses, and data are shifted in and out of the device, starting with the most significant bit. serial data input (si) is sampled on the first rising edge of serial clock (sck) after chip se lect (cs#) is driven low. then, the one- byte instruction code must be shifted in to the device, most significant bit first, on serial data input (si), each bit bein g latched on the rising edges of serial clock (sck). the instruction set is listed in ta b l e 5 . every instruction sequence starts with a one-byte instruction code. depending on the instruction, this might be followed by address bytes, or by data bytes, or by both or none. chip select (cs#) must be driven high after the last bit of the in - struction sequence has been shifted in. in the case of a read data bytes (read), read status register (rdsr), fast read (fast_read) and read id (read_id), the shifted-in instruction sequence is fol - lowed by a data-out sequence. chip sele ct (cs#) can be driven high after any bit of the data-out sequence is being shifted out to terminate the transaction. in the case of a page program (pp), sector erase (se), bulk erase (be), write status register (wrsr), write enable (wren), or write disable (wrdi) instruc - tion, chip select (cs#) must be driv en high exactly at a byte boundary, otherwise the instruction is rejected, and is not executed. that is, chip select (cs#) must driven high when the number of clock pulses after chip select (cs#) being driven low is an exact multiple of eight. all attempts to access the memory array during a write status register cycle, program cycle or erase cycle are ignored, and the internal write status register cycle, program cycle or erase cycle continues unaffected ta b l e 5 . instruction set. instruction description one-byte instruction code address bytes dummy byte data bytes status register operations wren write enable 06h (0000 0110) 0 0 0 wrdi write disable 04h (0000 0100) 0 0 0 wrsr write to status register 01h (0000 0001) 0 0 1 rdsr read from status register 05h (0000 0101) 0 0 1 to infinity read operations read read data bytes 03h (0000 0011) 3 0 1 to infinity fast_read read data bytes at higher speed 0bh (0000 1011) 3 1 1 to infinity read_id read id abh (1010 1011) 0 3 1 to infinity erase operations se sector erase d8h (1101 1000) 3 0 0 be bulk (chip) erase c7h (1100 0111) 0 0 0 program operations pp page program 02h (0000 0010) 3 0 1 to 256 dummy power savings mode operations sp software protect b9h (1011 1001) 0 0 0 res release from software protect abh (1010 1011) 0 0 0 release from software protect and read electronic signature abh (1010 1011) 0 3 1 to infinity
14 s25fl family (serial peripheral interface) 30167a+1 june 9, 2004 preliminary information write enable (wren) the write enable (wren) instruction ( figure 4 ) sets the write enable latch (wel) bit. the write enable latch (wel) bit must be set prior to every page program (pp), erase (se or be) and write status register (wrsr) instruction. the write enable (wren) instruction is entered by driving chip select (cs#) low, sending the instruction code, and then driving chip select (cs#) high. figure 4. write enable (wren) instruction sequence write disable (wrdi) the write disable (wrdi) instruction ( figure 5 ) resets the write enable latch (wel) bit. the write disable (wrdi) instruction is entered by driving chip select (cs#) low, sending the instruction code, and then driving chip select (cs#) high. the write enable latch (wel) bit is reset under the following conditions: ? power-up ? write disable (wrdi) instruction completion ? write status register (wrsr) instruction completion ? page program (pp) instruction completion ? sector erase (se) instruction completion ? bulk erase (be) instruction completion figure 5. write disable (wrdi) instruction sequence read status register (rdsr) the read status register (rdsr) instruction allows the status register to be read. the status register may be read at any time, even while a program, erase, or write status register cycle is in progress. when one of these cycles is in progress, it is recommended to check the write in progress (wip) bit before cs# sck si so high impedance instruction 01 23 4 5 67 0 1 2 34 5 6 7 sck si so high impedance instruction cs#
june 9, 2004 30167a+1 s25fl family (serial peripheral interface) 15 preliminary information sending a new instruction to the device. it is also possible to read the status reg - ister continuously, as shown in figure 6 . figure 6. read status register (rdsr) instruction sequence figure 7. status register format the status and control bits of th e status register are as follows: srwd bit: the status register write disable (s rwd) bit is operated in conjunc - tion with the write protect (w#) sign al. the status register write disable (srwd) bit and write protect (w#) signal allow the device to be put in the hard - ware protected mode (when the status re gister write disable (srwd) bit is set to 1, and write protect (w#) is driven low). in this mode, the non-volatile bits of the status register (srwd, bp1, bp0) become read-only bits and the write status register (wrsr) instruction is no longer accepted for execution. bp1, bp0 bits: the block protect (bp1, bp0) bits are non-volatile. they define the size of the area to be software protected against program and erase instruc - tions. these bits are written with the wr ite status register (wrsr) instruction. when one or both of the block protect (bp1, bp0) bits is set to 1, the relevant memory area (as defined in ta b l e 1 and ta b l e 2 ) becomes protected against page program (pp), and sector erase (se) instructions. the block protect (bp1, bp0) bits can be written provided that the hardware protected mode has not been set. the bulk erase (be) instruction is executed if, and only if, both block protect (bp1, bp0) bits are 0. wel bit: the write enable latch (wel) bit indicates the status of the internal write enable latch. when set to 1, the internal write enable latch is set; when set to 0, the internal write enable latch is reset and no write status register, pro - gram or erase instruction is accepted. instruction high impedance msb msb status register out status register out 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 7 6 5 4 3 2 10 7 6 5 4 3 2 1 0 7 so si sck cs# status register write disable block protect bits write enable latch bit write in pro g ress bit srwd 0 0 bp1 bp0 wel wip b7 b0
16 s25fl family (serial peripheral interface) 30167a+1 june 9, 2004 preliminary information wip bit: the write in progress (wip) bit indicates whether the memory is busy with a write status register, program or erase cycle. this bit is a read only bit and is read by executing a rdsr instruction. if this bit is 1, such a cycle is in progress, if it is 0, no such cycle is in progress. write status register (wrsr) the write status register (wrsr) instruction allows new values to be written to the status register. before it can be acce pted, a write enable (wren) instruction must previously have been executed. af ter the write enable (wren) instruction has been decoded and executed, the device sets the write enable latch (wel). the write status register (w rsr) instruction is entered by driving chip select (cs#) low, followed by the instruction code and the data byte on serial data input (si). the instruction sequence is shown in figure 8 . the write status register (wrsr) instructio n has no effect on bits b6, b5, b4, b1 and b0 of the status register. bits b6, b5 and b4 are always read as 0. chip select (cs#) must be driven high af ter the eighth bit of the data byte has been latched in. if not, the write status register (wrsr) instruction is not exe - cuted. as soon as chip select (cs#) is driven high, the self-timed write status register cycle (whose duration is t w ) is initiated. while the write status register cycle is in progress, the status register may still be read to check the value of the write in progress (wip) bit. the write in progress (wip) bit is 1 during the self-timed write status register cycle, and is 0 when it is completed. at some un - specified time before the cycle is completed, the write enable latch (wel) is reset. the write status register (wrsr) instruct ion allows the user to change the val - ues of the block protect (bp1, bp0) bits, to define the size of the area that is to be treated as read-only, as defined in ta b l e 1 and ta b l e 2 . the write status reg - ister (wrsr) instruction also allows the user to set or reset the status register write disable (srwd) bit in accordance with the write protect (w#) signal. the status register write disable (srwd) bit and write protect (w#) signal allow the device to be put in the hardware protected mode (hpm). the write status regis - ter (wrsr) instruction cannot be executed once the hardware protected mode (hpm) is entered. figure 8. write status register (wrsr) instruction sequence high impedance msb instruction status register in cs# sck si so 0 12 3 4 5 6 7 8 9 10 11 12 13 14 15
june 9, 2004 30167a+1 s25fl family (serial peripheral interface) 17 preliminary information ta b l e 6 . protection modes 5. as defined by the values in the block protect (bp1, bp0) bits of the status register, as shown in table 1 and table 2 . the protection features of the device are summarized in ta b l e 6 . when the status register write disable (srw d) bit of the status register is 0 (its initial delivery state), it is possible to write to the status register provided that the write enable latch (wel) bit has previously been set by a write enable (wren) instruction, regardless of the whether write protect (w#) is driven high or low. when the status register write disable (s rwd) bit of the status register is set to 1, two cases need to be considered, depending on the state of write protect (w#): ? if write protect (w#) is driven high, it is possible to write to the status reg- ister provided that the write enable latch (wel) bit has previously been set by a write enable (wren) instruction. ? if write protect (w#) is driven low, it is not possible to write to the status register even if the write enable latch (wel) bit has previously been set by a write enable (wren) instruction. (attempts to write to the status register are rejected, and are not accepted for execution). as a consequence, all the data bytes in the memory area that are software protected (spm) by the block protect (bp1, bp0) bits of the status register, are also hardware pro- tected against data modification. regardless of the order of the two even ts, the hardware protected mode (hpm) can be entered: ? by setting the status register write disable (srwd) bit after driving write protect (w#) low ? or by driving write protect (w#) low after setting the status register write disable (srwd) bit. the only way to exit the hardware protecte d mode (hpm) once entered is to pull write protect (w#) high. if write protect (w#) is permanently tied high, the hardware protected mode (hpm) can never be activated, and only the software protected mode (spm), using the block protect (bp1, bp0) bits of the status register, can be used. read data bytes (read) the device is first selected by driving chip select (cs#) low. the instruction code for the read data bytes (read) instruction is followed by a 3-byte address (ad - dress bits a23 to a18 are do n?t care), each bit being latched-in during the rising edge of serial clock (sck). then the memory contents, at that address, are w# signal srwd bit mode write protection of the status register protected area (note 1) unprotected area (note 1) 1 1 software protected (spm) status register is writeable (if the wren instruction has set the wel bit) the values in the srwd, bp1 and bp0 bits can be changed protected against page program and erase (se, be) ready to accept page program and sector erase instructions 1 0 0 0 0 1 hardware protected (hpm) status register is hardware write protected the values in the srwd, bp1 and bp0 bits cannot be changed protected against page program and erase (se, be) ready to accept page program and sector erase instructions
18 s25fl family (serial peripheral interface) 30167a+1 june 9, 2004 preliminary information shifted out on serial data output (so), ea ch bit being shifted out, at a frequency f sck , during the falling edge of serial clock (sck). the instruction sequence is shown in figure 9 . the first byte addressed can be at any location. the address is automatica lly incremented to the next higher ad - dress after each byte of da ta is shifted out. the whole memory can, therefore, be read with a single read data bytes (read) instruction. when the highest address is reached, the address counter rolls over to 00000h, allowing the read sequence to be continued indefinitely. the read data bytes (read) instruction is terminated by driving chip select (cs#) high. chip select (cs#) can be driven high at any time during data output. any read data bytes (read) instruction, while a program, erase, or write cycle is in progress, is rejected without having any effect on the cycle that is in progress. figure 9. read data bytes (read) instruction sequence read data bytes at higher speed (fast_read) the fast read (fast_read) instruction implemented in this device is compatible with industry standard fast read (fast_read) operations. the device is first se - lected by driving chip select (cs#) low. the instruction code for (fast_read) instruction is followed by a 3-byte address (a23-a0 for 2mbit devices) and a dummy byte, each bit being latched-in during the rising edge of serial clock (sck). then the memory contents, at that address, are shifted out on serial data output (so), each bit being shifte d out, at a maximum frequency f sck , during the falling edge of serial clock (sck). the instruction sequence is shown in figure 10 . the first byte addressed can be at any location. the address is automatically incremented to the next higher ad - dress after each byte of da ta is shifted out. the whole memory can, therefore, be read with a single (fast_read) instruction. when the highest address is reached, the address counter rolls over to 00000h, allowing the read sequence to be continued indefinitely. the (fast_read) instruction is terminated by driving chip select (cs#) high. chip select (cs#) can be driven high at any time during data output. any instruction 24-bit address high impedance msb msb data out 1 data out 2 0 31 32 33 34 35 36 37 38 39 30 23 28 10 9 8 7 6 5 4 3 2 1 7 6 5 23 22 21 4 3 2 1 0 3 2 1 0 7 so si sck cs#
june 9, 2004 30167a+1 s25fl family (serial peripheral interface) 19 preliminary information (fast_read) instruction, while an erase, program or write cycle is in progress, is rejected without having any effects on the cycle that is in progress. figure 10. fast read (fast_read) instruction sequence page program (pp) the page program (pp) instruction allows bytes to be programmed in the memory (changing bits from 1 to 0). before it can be accepted, a write enable (wren) instruction must previously have been executed. after the write enable (wren) instruction has been decoded, the device sets the write enable latch (wel). the page program (pp) instruction is ent ered by driving chip select (cs#) low, followed by the instruction code, three add ress bytes and at least one data byte on serial data input (si). chip select (cs#) must be driven low for the entire duration of the sequence. the instruction sequence is shown in figure 11 . if more than 256 bytes are sent to the device, the addressing will wrap to the beginning of the same page, previously latched data are discarded and the last 256 data bytes are guaranteed to be programmed correctly within the same page. if fewer than 256 data bytes are se nt to device, they are correctly pro - grammed at the requested addresses with out having any effects on the other bytes of the same page. chip select (cs#) must be driven high af ter the eighth bit of the last data byte has been latched in, otherwise the page program (pp) instruction is not executed. as soon as chip select (cs#) is driven high, the self-timed page program cycle (whose duration is t pp ) is initiated. while the page program cycle is in progress, the status register may be read to check the value of the write in progress (wip) bit. the write in progress (wip) bit is 1 during the self-timed page program cycle, and is 0 when it is completed. at some unspecified time before the cycle is com - pleted, the write enable latch (wel) bit is reset. a page program (pp) instruction applied to a page that is protected by the block protect (bp1, bp0) bits (see ta b l e 1 and ta b l e 2 ) is not executed. cs# sck si so instruction 24-bit address dummy byte high impedance data out 1 data out 2 msb msb 01 2 34 56 7 8 9 10 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 23 22 21 3 2 1 0 7 654 3 2 1 0 7 6 5 4 3 210 7
20 s25fl family (serial peripheral interface) 30167a+1 june 9, 2004 preliminary information figure 11. page program (pp) instruction sequence sector erase (se) the sector erase (se) instruction sets to 1 (ffh) all bits inside the chosen sector. before it can be accepted, a write enable (wren) instruction must previously have been executed. after the write enable (wren) instruction has been de - coded, the device sets the write enable latch (wel). the sector erase (se) instruction is entered by driving chip select (cs#) low, followed by the instruction code, and three address bytes on serial data input (si). any address inside the sector (see ta b l e 1 and ta b l e 2 ) is a valid address for the sector erase (se) instruction. chip select (cs#) must be driven low for the entire duration of the sequence. the instruction sequence is shown in figure 12 . chip select (cs#) must be driven high aft er the eighth bit of the last address byte has been latched in, otherwise the sector erase (se) instruction is not executed. as soon as chip select (cs#) is driven high, the self-timed sector erase cycle (whose duration is tse) is initiated. while the sector erase cycle is in progress, the status register may be read to check the value of the write in progress (wip) bit. the write in progress (wip) bit is 1 during the self-timed sector erase cycle, and is 0 when it is completed. at some unspecified time before the cycle is com - pleted, the write enable latch (wel) bit is reset. a sector erase (se) instruction applied to any memory area that is protected by the block protect (bp1, bp0) bits (see ta b l e 1 and ta b l e 2 ) is not executed. 0 34 33 32 31 30 29 28 10 9 8 7 6 5 4 3 2 1 35 36 37 38 39 46 45 44 43 42 41 40 47 48 49 50 51 52 53 54 55 2073 2072 2076 2075 2074 2079 2078 2077 23 22 21 3 21 07 6 5 43 2 1 0 data byte 1 24-bit address instruction data byte 2 data byte 3 data byte 256 msb msb msb msb msb sck si sck si 7 65 4 3 2 1 0 76 54 321 0 7 6 5 43210 cs# cs#
june 9, 2004 30167a+1 s25fl family (serial peripheral interface) 21 preliminary information figure 12. sector erase (se) instruction sequence bulk erase (be) the bulk erase (be) instruction sets to 1 (ffh) all bits inside the entire memory. before it can be accepted, a write enable (wren) instruction must previously have been executed. after the write enable (wren) instruction has been de - coded, the device sets the write enable latch (wel). the bulk erase (be) instruction is entered by driving chip select (cs#) low, fol - lowed by the instruction code, on serial data input (si). no address is required for the bulk erase (be) instruction. chip select (cs#) must be driven low for the entire duration of the sequence. the instruction sequence is shown in figure 13 . chip select (cs#) must be driven high aft er the eighth bit of the last address byte has been latched in, otherwise the bulk erase (be) instruction is not executed. as soon as chip select (cs#) is driven high, the self-timed bulk erase cycle (whose duration is t be ) is initiated. while the bulk erase cycle is in progress, the status register may be read to check the value of the write in progress (wip) bit. the write in progress (wip) bit is 1 during the self-timed bulk erase cycle, and is 0 when it is completed. at some unspecified time before the cycle is com - pleted, the write enable latch (wel) bit is reset. a bulk erase (be) instruction is executed only if both the block protect (bp1, bp0) bits (see ta b l e 1 and ta b l e 2 ) are set to 0. the bulk erase (be) instruction is ig - nored if one or more sectors are protected. cs# sck si instruction 24 bit address 01 2 3 4 5 6 7 8 9 10 28 29 30 31 23 22 21 3 2 1 0 msb
22 s25fl family (serial peripheral interface) 30167a+1 june 9, 2004 preliminary information figure 13. bulk erase (be) instruction sequence software protect (sp) the software protect (sp) instruction implemented in this device is compatible with industry-standard software protect (s p) operation. for this device, this in - struction has no real function since the standby current (i sb ) on this device is the same as the deep power-down current in our competitor's devices. it is recommended that the standard stan dby mode be used for the lowest power current draw, as well as the software protec t (sp) as an extra software protection mechanism when this device is not in active use. in this mode, the device ignores all write, program and erase instructions. chip select (cs#) must be driven low for the entire duration of the sequence. the software protect (sp) instruction is entered by driving chip select (cs#) low, followed by the instruction code on serial data input (si). chip select (cs#) must be driven low for the entire duration of the sequence. the instruction sequence is shown in figure 14 . driving chip select (cs#) high after the eighth bit of the instruction code has been latched in deselects the device, and puts the device in the standby mode (if there is no internal cycle currently in progress). as soon as chip select (cs#) is driven high, it requires a delay of t sp currently in progress before software pro - tect mode is entered. once the device has entered the softwa re protect mode, all instructions are ig - nored except the release from software protect (res) or read id (read_id) instruction. the release from software protect and read electronic signature (res) instruction also allows the electronic signature of the device to be output on serial data output (so). the software protect mode automatically stops at power-down, and the device always powers-up in the standby mode. 01 2 4 56 7 instruction cs# sck si 3
june 9, 2004 30167a+1 s25fl family (serial peripheral interface) 23 preliminary information any software protect (sp) instruction, while an erase, program or wrsr cycle is in progress, is rejected without having any effect on the cycle in progress. figure 14. software protection (sp) instruction sequence release from software protect (res) the release from software protect (res) inst ruction provides the only way to exit the software protect mode. once the device has entered the software protect mode, all instructions are ignored except the release from software protect (res) instruction. the release from software protect (res) in struction is entered by driving chip select (cs#) low, followed by the instruction code on serial data input (si). chip select (cs#) must be driven low for the entire duration of the sequence. the instruction sequence is shown in figure 15 . driving chip select (cs#) high after the 8-bit instruction byte has been received by the device, but before the whole of the 8-bit electronic signature has been transmitted for the first time, still insures that the device is put into standby mode. if the device was previously in the software protect mode, though, the transition to the stand-by power mode is delayed by t res , and chip select (cs#) must remain high for at least t res(max) , as specified in ta b l e 7 . once in the stand- by power mode, the device waits to be se lected, so that it can receive, decode and execute instructions. cs# sck si standby mode software protect mode instruction 0 1 234 56 7 t sp
24 s25fl family (serial peripheral interface) 30167a+1 june 9, 2004 preliminary information figure 15. release from software protect (res) instruction sequence release from software protection and read electronic signature (res), and read id (read_id) once the device has entered sp mode, all instructions are ignored except the res instruction. the res instruction can also be used to read the 8-bit electronic sig - nature of the device on the so pin. the res instruction always provides access to the electronic signature of the device (except while an erase, program or wrsr cycle is in progress), and can be applied even if sp mode has not been en - tered. any res instruction executed while an erase, program or wrsr cycle is in progress is not decoded, and has no effect on the cycle in progress. the read id (read_id) instruction can be used to read, on serial data output (so), the 8-bit electronic signature of the device. except while an erase, program or write status register cycle is in progress, the read id (read_id) instruction always provides access to the electronic signa - ture of the device, and can be applied even if the software protect mode has not been entered. any read id (read_id) instruction while an erase, program or write status reg - ister cycle is in progress, is not decoded, and has no effect on the cycle that is in progress. the device features an 8-bit electronic signature, whose value for the s25fl002d is 11h, s25fl002d is 10h. this can be read using read id (read_id) instruction. the device is first selected by driving chip select (cs#) low. the instruction code is followed by 3 dummy bytes, each bit bein g latched-in on serial data input (si) during the rising edge of s erial clock (sck). then, the 8-bit electronic signature, stored in the memory, is shifted out on serial data output (so), each bit being shifted out during the falling edge of serial clock (sck). the instruction sequence is shown in figure 16 . the read id (read_id) instruction is terminated by driving chip select (cs#) high after the electronic signature ha s been read at least once. sending addi - cs# sck si 0 1 23 4 5 6 7 instruction software protect mode t res standby mode
june 9, 2004 30167a+1 s25fl family (serial peripheral interface) 25 preliminary information tional clock cycles on serial clock (sck), while chip select (cs#) is driven low, causes the electronic signature to be output repeatedly. when chip select (cs#) is driven high, the device is put in the stand-by power mode. if the device was not previously in the software protect mode, which oc - curs when the read id (read_id) instruction is initiated, the transition to the stand-by power mode is immediate. if th e device was previously in the software protect mode, though, the transition to the standby mode is delayed by t res , and chip select (cs#) must remain high for at least t res(max) , as specified in ta b l e 9 . once in the stand-by power mode, the de vice waits to be selected, so that it can receive, decode and execute instructions. figure 16. release from software protection and read elec tronic signature (res), and read id (read_id) instruction sequence cs# sck si so 3 dummy bytes high impedance msb software protect mode standby mode 0 1 2 3 4567 8 9 10 28 29 30 31 32 33 34 35 36 37 38 electronic id out instruction t res 23 22 21 3 2 10 7 654 32 1 0 msb
26 s25fl family (serial peripheral interface) 30167a+1 june 9, 2004 preliminary information power-up and power-down the device must not be selected at pow er-up or power-down (that is, cs# must follow the voltage applied on v cc ) until v cc reaches the minimum correct value, as follows: ? v cc (min) at power-up, and then for a further delay of t pu (as described in ta b l e 7 ) ? v ss at power-down a simple pull-up resistor on chip select (cs#) can usually be used to insure safe and proper power-up and power-down. to avoid data corruption and inadvertent write operations during power up, a power on reset (por) circuit is included. the logic inside the device is held reset while v cc is less than the por threshold value (v por ). all operations are disabled, and the device does not respond to any instructions. the device ignores all instructions until a time delay of t pu (as described in ta b l e 7 ) has elapsed after the moment that v cc rises above the minimum v cc thresh - old. however, correct operation of the device is not guaranteed if by this time v cc is still below v cc (min). no read, write status register, program or erase instruc - tions should be sent until t pu after v cc reaches the minimum v cc threshold. at power-up, the device is in standby mode (not software protect mode) and the wel bit is reset. normal precautions must be taken for supply rail decoupling to stabilize the v cc feed. each device in a system should have the v cc rail decoupled by a suitable capacitor close to the package pins (this ca pacitor is generally of the order of 0.1 f). at power-down, when v cc drops from the operating voltage to below the mini - mum v cc threshold, all operations are disabled and the device does not respond to any instructions. (the designer needs to be aware that if a power-down occurs while a write, program or erase cycle is in progress, data corruption can result.) figure 17. power-up timing v cc v cc (max) v cc (min) *note: program, erase, and write commands are not allowed and are not recommended during this period, as the state of the device operation is unknown during t pu. device fully accessible time t pu v por reset state of the device *note
june 9, 2004 30167a+1 s25fl family (serial peripheral interface) 27 preliminary information ta b l e 7 . power-up timing initial delivery state the device is delivered with all bits set to 1 (each byte contains ffh). the status register contains 00h (all status register bits are 0). maximum rating stressing the device above the rating listed in the absolute maximum ratings section below may cause p ermanent damage to the device. these are stress rat - ings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability absolute maximum ratings ambient storage temperature . . . . . . . . . . . . . . . . . . . . . ?65c to +150c voltage with respect to ground: all inputs and i/os. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ?0.3 v to 4.5 v operating ranges ambient operating temperature (t a ) commercial . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0c to +70c industrial . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ?40c to +85c positive power supply voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2.7 v to 3.6 v operating ranges define those limits between which functionality of the device is guaranteed. symbol parameter min max unit t pu v cc (min) to cs# low 2 ms v por por threshold value 2.2 2.4 v
28 s25fl family (serial peripheral interface) 30167a+1 june 9, 2004 preliminary information dc characteristics this section summarizes the dc and ac characteristics of the device. designers should check that the operating conditions in their circuit match the measure - ment conditions specified in the test specifications in ta b l e 8 , when relying on the quoted parameters. cmos compatible note: 1. typical values are at t a = 25 c and 3.0 v. parameter description test conditions (note 1) min typ. max unit v cc supply voltage 2.7 3 3.6 v i cc1 v cc active read current sck = 0.1 v cc /0.9v cc 25 mhz v cc = 3.0v 9 12 ma i cc2 v cc active page program current cs# = v cc 10 16 ma i cc3 v cc active wrsr current cs# = v cc 20 ma i cc4 v cc active sector erase current cs# = v cc 20 ma i cc5 v cc active bulk erase current cs# = v cc 20 ma i sb standby current cs# = v cc = 3.0 v 1 3 a i li input leakage current v in = gnd to v cc 1 a i lo output leakage current v in = gnd to v cc 1 a v il input low voltage ?0.3 0.3 v cc v v ih input high voltage 0.7 v cc v cc + 0.5 v v ol output low voltage i ol = 1.6 ma, v cc = v cc min 0.4 v v oh output high voltage i oh = ?0.1 ma v cc ? 0.2 v
june 9, 2004 30167a+1 s25fl family (serial peripheral interface) 29 preliminary information test conditions figure 18. ac measurements i/o waveform ta b l e 8 . test specifications symbol parameter min max unit c l load capacitance 30 pf input rise and fall times 5 ns input pulse voltage 0.2 v cc to 0.8 v cc v input and output timing reference voltages 0.3 v cc to 0.7 v cc v 0.8 v cc 0.2 v cc 0.7 v cc 0.3 v cc input levels input and output timing reference levels
30 s25fl family (serial peripheral interface) 30167a+1 june 9, 2004 preliminary information ac characteristics ta b l e 9 . ac characteristics note: 1. typical program and erase time assume the following conditions: 25 c , v cc = 3.0v; 10,000 cycles; checkerboard data pattern. 2. under worst-case conditions of 90 c ; v cc = 2.7v; 100,000 cycles. 3. not 100% tested 4. both for read and fast_read symbol parameter min typ max unit f sck (note 4) sck clock frequency 25 mhz t crt clock rise time (slew rate) 0.1 v/ns t cft clock fall time (slew rate) 0.1 v/ns t wh sck high time 18 ns t wl sck low time 18 ns t cs cs# high time 100 ns t css (note 3) cs# setup time 10 ns t csh (note 3) cs# hold time 10 ns t hd (note 3) hold# setup time 10 ns t cd (note 3) hold# hold time 10 ns t hc hold setup time (relative to sck) 10 ns t ch hold hold time (relative to sck) 10 ns t v output valid 0 15 ns t ho output hold time 0 ns t hd:dat data in hold time 5 ns t su:dat data in setup time 5 ns t lz (note 3) hold# to output low z 15 ns t hz (note 3) hold# to output high z 20 ns t dis (note 3) output disable time 15 ns t wps (note 3) write protect setup time 20 ns t wph (note 3) write protect hold time 100 ns t res release sp mode 1.0 s t sp cs# high to software protect mode 3.0 s t w write status register time 1.6 15 (note 2) ms t pp (note 1) page programming time 6 (note 1) 10 (note 2) ms t se sector erase time 512 kb sector (s25fl002d) 0.5 (note 1) 0.8 (note 2) sec 256 kb sector (S25FL001D) 0.25 (note 1) 0.4 (note 2) sec t be bulk erase time 1 mb device 1.0 (note 1) 1.6 (note 2) sec 2 mb device 2.0 (note 1) 3.2 (note 2)
june 9, 2004 30167a+1 s25fl family (serial peripheral interface) 31 preliminary information ac characteristics figure 19. spi mode 0 (0,0) input timing figure 20. spi mode 0 (0,0) output timing cs# sck si so t csh t css t csh t css t crt t cft msb in lsb in high impedance t su:dat t hd:dat t cs cs# sck so lsb out t wh t wl t dis t v t ho t v t ho
32 s25fl family (serial peripheral interface) 30167a+1 june 9, 2004 preliminary information ac characteristics figure 21. hold# timing figure 22. write protect setup and hold timing during wrsr when srwd=1 t ch t hz t cd t hd t hc t lz cs# sck so si hold# w# cs# sck si so high impedance t wps t wph
june 9, 2004 30167a+1 s25fl family (serial peripheral interface) 33 preliminary information physical dimensions s08 narrow?8-pin plastic small outline 150mils body width package
34 s25fl family (serial peripheral interface) 30167a+1 june 9, 2004 preliminary information physical dimensions s08 wide?8-pin plastic small outline 208mils body width package
june 9, 2004 30167a+1 s25fl family (serial peripheral interface) 35 preliminary information s08 wide?8-pin plastic small outline 208mils body width package (continued) design note: this note is for the s25fl002d device only. it is recommended that during pcb layout, pads be placed on the board to ac - commodate both spansion?s so-8 narrow and wide footprints. this will allow for a smooth upgrade path to our 4mb and 8mb spi devices, without the need to re- layout the board. in order to simplify layout, only one set of pads needs to be added to the board to accommodate the 208 mils so-8 wide package. because the pinouts of both the narrow and wide footprint parts are the same, no jumpers need to be placed on the board.
36 s25fl family (serial peripheral interface) 30167a+1 june 9, 2004 preliminary information physical dimensions 8-contact wson (6mm x 5mm) leadless package
june 9, 2004 30167a+1 s25fl family (serial peripheral interface) 37 preliminary information revision summary revision a (november 7, 2003) initial release. revision a+1 (june 9, 2004) minor corrections, updated 8- pin soic package diagram. updated notes for table 9 . ac characteristics. removed 512kb offering. removed page erase (pe) functionality. added the wide 8-pin so (208mils) package. added design note for 2mb. added the 8-contact wson (6mm x 5mm) leadless package.
38 s25fl family (serial peripheral interface) 30167a+1 june 9, 2004 preliminary information trademarks and notice the contents of this document are subject to change without notice. this document may contain information on a spansion product under development by fasl llc. fasl llc reserves the right to change or discontinue work on any product without notice. the information in this docu ment is provided as is without warranty or guarantee of any kind as to its accuracy, completeness, operability, fitness for particular purpose, mercha ntability, non-infringement of third-party rights, or any other warranty, express, implied, or statutory. fasl llc assumes no liability for any damages of any kind arising out of the use of the information in this document. copyright ? 2004 fasl llc. all rights reserved. spansion, the spansion logo, mirrorbit, comb inations thereof, and expressflash are trademarks of fasl llc. other company and pr oduct names used in this publication are for identification purposes only and may be trademarks of their respective companies.

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